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Facilitating IP Reuse: An Alternative Technology
Abstract: A system-in-a-package system in package (SiP) approach to reusing intellectual property costs less to produce, saves time in design and testing, and improves performance.
By David Sherman, Vice President of Engineering, Alpine Microsystems Inc., Campbell, California
IC designers need the ability to freely combine and reuse IP
Designing new products is easier when you don’t have to reinvent each detail from scratch. That’s the guiding principle behind the growing libraries of intellectual property (IP)—by reusing proven design methodologies you can quickly and cost effectively create new generations of systems. The emphasis, however, has to be on "quickly" and "cost effectively." If the approach you take to reusing the IP requires too much time to integrate and test, or if the system becomes too expensive to produce, you lose everything you gained.
Even the first "PASS" doesn’t guarantee success. Often a design has to fit into a rapidly evolving niche of its own. Many designs can’t wait for component updates but need to get to market as soon as possible. They have to be flexible enough to upgrade rapidly changing component IC’s as they become available. The processor, for instance, may take two years for a major revision, but the memory might undergo a shrink every nine months while the ASIC or ASSP changes with every bus standard revision. See Figure 1. You have to plan for this flexibility. If you lock yourself into too rigid an approach, updating your design might force an expensive and time-consuming restart from square one.
(Graphic of turns from "SiP versus SoC")
Figure1: Only flexible integration strategies for the reuse of intellectual property (IP) can take advantage of different integrated circuit (IC) upgrade schedules to improve performance.
Conventional technologies, such as SoC, can complicate reuse
The problem is that conventional approaches to combining IP introduce unnecessary complexity and cost into chip design and development. These complications can actually discourage reuse. The goal, after all, is to solve problems through IP reuse, not to create new ones.
System-on-a-chip (SoC) is the best known methodology for combining core IP into new technology—but it’s not the only way. The SoC approach has severe drawbacks that make it unsuitable for all but the highest-volume applications. These limitations include: the lack of component upgrade flexibility; addition of unnecessary levels of complexity that increase component cost, design time, and test time; and increased restrictions on printed-circuit board layout, performance, and power dissipation. For most applications, cell-based design with SoC has already reached a plateau in terms of price, performance and time to market and is at the point of diminishing returns.
Consider just the mask cost for a new SoC. Standard wafer processes are optimized for either logic or memory. Since most SoC designs mix both technologies, they require additional mask steps. Accommodating different analog and digital geometries adds even more mask steps. These complexities increase die size, complicate wafer processing, and raise defect density. The cost of a typical SoC mask set in 0.18 is already $350K, but is expected to reach $500K at a 0.13 process, exceed $1M at 0.1 and hit $4M at 0.07. If a product has a lifetime volume of 100K units, for example, at 0.1um lithography node, and masks at the $1M level, then each unit will carry a $10 premium just for the cost of the masks.
As processes shrink and design become more complex, the time necessary to design a SoC device is much longer than the time required for designing the IP coresCs. This is because most SoC designs require a custom integration with unique "buried" interfaces. Test access is compromised, and it is difficult to ensure that they will work together without interference. If digital-switching noise, for example, is injected into the substrate, it will be coupled into sensitive analog circuits. Long line delays can easily exceed the operating frequency of the SoC further complicating the routing and timing closure. The EDA tools available to predict and control these complex interactions are limited in scope, expensive, and time consuming to use.
Production testing is also compromised. Expensive test gear has to be mu as increasing time in testingltiplexed, resulting in poorer utilization and higher cost. Frequently the OEM customer faces rising system cost to route high pin count components on multi-layer printed circuit boards to compensate for noise, jitter and loss of signal integrity.
An alternative approach—system-in-a package—simplifies IP reuse
The search for better alternatives has lead to an emerging new generation of system-level integrationpackaging, termed "system-in-a-packagein-package" (SiP). The SiP approach uses IC processing technology to create high-density substrates capable of integrating multiple IP blocks with single package components. See Figure 2. This approach maintains design simplicity by allowing the creation of separately manufactured IP blocks and ensuring component upgrade flexibility.
(Drawing of SiP.)
Figure 2: A system-in-a-packagein-package (SiP) approach expresses IP by combining multiple ICs and discrete components into single packages using IC processing technology.
The higher integration capacity of SiP reduces the number of individually packaged devices in the system. This reduces both the size and the routing complexity of the PC board. Designers can also reduce or eliminate many passive components, such as resistive terminators and local bypass capacitors. SiPs provide an optimum middle ground occupy an attractivebetween thick film/PCB technology and single chip integrationSOCs. See Figure 3. The SiP approach achieves the final assembly advantages of a SoC while retaining the design and manufacturing advantages of separately packaged parts.
(System Integration Comparison—from whySiP.html )
Figure 3: Thick film/PCB is too low density and too slow. SoC is limited in complexity by cost and design time. SiP offers higher performance at lower cost.
SiPs give designers an edge in design, performance and system cost
In a SiP approach, you select IP components that are optimized to minimize manufacturing costs and to take advantage of the high-speed and high I/O density characteristics of the substrate. By partitioning functions like memory, logic, or analog into separate die wafer, fabrication becomes simpler, die size is reduced, and wafer yield increases. IP handled as die can be fully tested and characterized, streamlining the design phase.
In addition to reduced die area through partitioning, I/O driver size and voltage can be reduced for internal interconnect. Array pads allow a much larger number of I/O ports to widen busses and eliminate multiplexed duplex busses. Outside of the package, interfaces between die in SiPs are also buried, but there is an important distinction. The separate dies that comprise the SiP can be tested by standard test flows. The only additional tests necessary for buried busses are JTAG Extest, commonly used on state-of-the-art PC board designs.
Another significant difference between system-on-chip and system-in-package methodologies is the benefit that SiP technology brings to system-level interconnect. See Figure 4. These include lower power and noise, which, in turn, allow higher operating frequency and higher bandwidth. For example, in Alpine Microsystems' (Campbell, CA) SiP approach, the substrate is attached to the PC board using an area array packaging technique that provides a very low inductance path from the PC board to the ICs and also improves heat dissipation.
(Figure 2 from SiP vs. SoC)
Figure 4. Cross-section of SiP system interconnect. SiP technology allows small I/O drivers to be placed closer to their functional source reducing on chip routing. More I/O ports are also possible allowing on-chip multiplexing to be eliminated. The effect is to lower power and noise in system-level interconnect.
This methodology is based on a patented Microboard substrate, developed with IC processing techniques that allow very fine line width and via geometry. The Microboard substrate utilizes a copper on low-k dielectric interconnect that offers very high routing resources with high-speed/low noise 50-Ohm signal paths. Solder bump technology provides ultra-low (less than 50 pH) inductance connections.
SiP flexibility facilitates IP Reuse
Designers can preserve IP blocks intact by "cloning" duplex existing busses and defaulting them to unidirectional operation. Many I/Os are now available with programmable drive strength and voltage. This means that existing IP can achieve significant power and speed benefits by driving a lower swing signal, as long as off-module interfacing isn't required. Ideally, once a system designer has adopted a SiP approach, he or she can create co-designs that comprehend both on-die and off-die bus design to maximize benefits.
Once designers can treat off-die busses and on-die SoC busses similarly, they remove many of the barriers to architectural innovation. They can drive down cost by defining a bus that suitably intersects the routing density of both the SiP and the on-die density and then re-partitioning the system. For instance, they can use this to shift delay the integration ofa level of cache hierarchy from the processor dieby one process generation or more, reserving "expensive" transistors in the microprocessor process for logic, while moving to a readily available, lower cost SRAM die.SRAM vendors. Busses or groups of busses in the range of 512 bits wide fit easily in the area of interconnect density overlap for on-die and off-die busses.
Summary
The advantages of reusing intellectual property is clear; the problem is how to support the use of IP in creating cost effective hybrid systems. Popular technologies like system on a chip (SoC) actually raise complexity and cost for most applications. System in a package (SiP) is a very attractive alternative that occupies a "sweet spot" between SoC and traditional, separately packaged parts. SiP provided similar performance benefits to SoC, including lower power, higher speed, and smaller footprint, while avoiding the high cost of increased fab and testing. The flexibility inherent in the SiP approach avoids time-to-market delays by allowing component ICs to be easily updated. Finally, its ability to adapt and "clone" buses allows simpler, less expensive use of IP cores.
David Sherman is vice president of engineering for Alpine Microsystems, Inc. Formerly senior staff engineer at Cirrus Logic. Before Cirrus, he was also the founder and director of hardware engineering for Shographics. David began his career as an engineer at Atari Games.
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